Low-Temperature Coefficient of Thermal Expansion (CTE) Testing for IC Substrates

Low-temperature coefficient of thermal expansion (CTE) testing evaluates how IC package substrates dimensionally contract and expand across sub-zero temperature ranges, typically from -65°C up to +25°C. This test is essential for verifying the reliability of semiconductor packaging in automotive, aerospace, and outdoor telecommunications applications, where CTE mismatch between silicon die, substrate, and PCB drives solder joint fatigue and interfacial delamination. Accurate low-temperature CTE data provides critical inputs for material selection, finite element reliability modeling, and qualification to industry standards such as ASTM E831 and IPC-TM-650.

Technical Overview

IC substrates (package substrates) provide the electrical, thermal, and mechanical interconnection between a semiconductor die and the printed circuit board. Because finished electronic assemblies routinely experience sub-zero environments, such as cold-soak in automotive electronics at -40°C, military exposure at -55°C, and cryogenic conditions in space systems, the coefficient of thermal expansion of the substrate must be characterized at low temperature, not only at elevated temperature. Low-temperature CTE testing quantifies the linear dimensional change of a substrate per degree of temperature change over a defined sub-ambient window, with results expressed in parts per million per degree Celsius (ppm/°C).

The fundamental reliability concern is CTE mismatch. A silicon die contracts at approximately 2.6 ppm/°C, while a typical organic substrate core contracts at 10 to 17 ppm/°C in-plane and a standard PCB at 14 to 17 ppm/°C. During cold excursions, this differential contraction generates significant shear strain in solder bumps and ball-grid-array joints, tensile stress in low-k dielectric layers, and hoop stress in copper vias. Over repeated temperature cycles, these stresses produce joint fatigue cracking, corner delamination, pad lifting, and warpage instability. Low-temperature CTE measurements supply the material constants required for finite element analysis (FEA) and for reliability qualification aligned with AEC-Q100 and MIL-STD-883 style temperature cycling profiles.

Testing Samples

Organic BT Epoxy Core Substrates

Bismaleimide-triazine (BT) epoxy substrates reinforced with glass fabric are the most widely tested sample type. The woven glass cloth constrains in-plane expansion, yielding X/Y CTE values of approximately 12 to 16 ppm/°C, while the resin-dominated Z-axis may exceed 40 ppm/°C below the glass transition temperature. Both raw core laminate and patterned coupons with production copper balance are evaluated, since copper density shifts the effective CTE.

Ajinomoto Build-Up Film (ABF) Substrates

Build-up substrates using ABF dielectric layers support fine-line redistribution wiring for flip-chip ball-grid-array (FCBGA) packages. Because these substrates are used in large-body, high-density packages, low in-plane CTE targets below 10 ppm/°C are common. Low-temperature testing verifies that the film layers and microvia stacks remain dimensionally stable and free of hysteresis after repeated cold cycling.

Ceramic Substrates

Alumina (approximately 6.5 to 7 ppm/°C), aluminum nitride (approximately 4.5 ppm/°C), and low-temperature co-fired ceramic (LTCC) substrates are tested for hermetic, high-power, and RF packaging. Their inherently low and stable CTE at low temperature makes them suitable for wide-temperature-span applications, and testing confirms lot-to-lot consistency of the ceramic composition.

Glass-Core and Silicon Interposer Substrates

Glass cores (3 to 9 ppm/°C depending on glass composition) and silicon interposers (approximately 2.6 ppm/°C) are engineered to closely match the die CTE for 2.5D and 3D advanced packaging. Low-temperature testing is particularly important for these materials because their reliability benefit depends on maintaining near-silicon expansion behavior all the way down to the coldest operating point.

Test Coupons and Finished Package Substrates

In addition to raw laminate panels qualified to IPC-4101 slash sheets, testing is performed on etched coupons, bare package substrates, and assembled substrate samples. Finished substrates reveal the effective thermomechanical response of the composite structure, including core, build-up layers, copper planes, and solder mask, which cannot be fully predicted from raw material data alone.

Testing Items

• In-plane (X and Y axis) CTE below Tg, measured over defined low-temperature windows such as -65°C to -40°C, -40°C to 0°C, and 0°C to +25°C.
• Through-thickness (Z-axis) CTE at low temperature, which governs via barrel strain, microvia integrity, and pad lifting.
• Glass transition temperature (Tg) and CTE above Tg (alpha-2), reported alongside the low-temperature alpha-1 value for complete material characterization.
• Effective composite CTE of patterned substrates, accounting for copper distribution and layer stack-up.
• CTE hysteresis and dimensional drift across repeated cold cycles, used as an indicator of microcracking or irreversible damage.
• In-plane anisotropy arising from glass weave distortion, comparing warp and fill directions.
• Cold-end dimensional contraction data used to correlate with low-temperature warpage measurements.

Testing Methods

Thermomechanical Analysis (TMA)

TMA is the primary method, performed in accordance with ASTM E831 and IPC-TM-650 method 2.4.24. A specimen, typically 3 to 10 mm in the measurement direction for in-plane testing or 0.3 to 3 mm thick for Z-axis testing, is placed under a low-force expansion probe inside a fused silica stage. The furnace is cooled with liquid nitrogen or a mechanical refrigeration system, purged with helium to ensure uniform heat transfer at sub-zero temperatures. After an equilibrium hold at the cold end point, the temperature is ramped at 3 to 5°C/min, and the slope of the displacement-versus-temperature curve yields the CTE over the specified sub-ambient interval.

Push-Rod Dilatometry

Dilatometry per ASTM E228 and ASTM D696 uses a fused silica dilatometer with longer specimens, and ASTM D696 is specifically defined for the -30°C to +30°C range, making it well suited to low-temperature plastics and laminate evaluations. The method offers excellent precision for average in-plane CTE and serves as a cross-check for TMA results.

Strain Gauge Method

Precision bonded strain gauges with self-temperature compensation can be applied directly to finished package substrates and large panels. A matching dummy gauge on a reference material with known CTE compensates for apparent strain, allowing effective CTE measurement of complex, copper-patterned structures that are difficult to fixture in a TMA.

Optical and Digital Image Correlation (DIC) Methods

Non-contact optical techniques capture full-field in-plane strain inside an environmental chamber using speckle-pattern imaging or interferometry at discrete cold-soak setpoints. DIC is valuable for mapping local CTE variation near dense via arrays, board edges, and die shadow regions, and for measuring very low expansion coefficients approaching that of glass and silicon.

Specimen Conditioning and Test Procedure

Specimens are baked at 105°C to 125°C for one to two hours to remove absorbed moisture, since residual moisture distorts sub-zero expansion readings. The instrument is calibrated at low temperature using certified reference materials such as fused silica, copper, and aluminum. A typical profile cool-soaks at -65°C for 15 to 30 minutes, ramps to +25°C, and repeats for two to three cycles so that hysteresis and repeatability can be assessed. The final report presents alpha-1 CTE for each temperature interval, Tg, hysteresis behavior, and specimen orientation relative to the glass weave.

Applications

Low-temperature CTE test data for IC substrates directly supports qualification and design activities across the electronics industry. Key applications include:

• Automotive semiconductor packaging qualified to AEC-Q100 Grade 1 or Grade 0, where assemblies must survive -40°C cold-start exposure and repeated thermal cycling.
• Outdoor 5G base stations and telecommunications infrastructure subjected to severe winter climates and daily temperature swings.
• Aerospace, defense, and space electronics, where substrates must retain dimensional stability from -55°C down to cryogenic temperatures.
• High-performance computing and 2.5D/3D packaging, where interposer and substrate CTE control protects fine-pitch microbumps during cold excursions.
• Material selection and supplier incoming inspection against IPC-4101 and customer-specific CTE specifications.
• Finite element simulation inputs and solder joint lifetime prediction for temperature cycling profiles such as JEDEC JESD22-A104 Condition B through G.
• Failure analysis, comparing CTE hysteresis before and after temperature cycling to detect latent laminate damage.

FAQ

• Why must CTE be measured at low temperature rather than only from room temperature upward? Organic resins and laminate composites exhibit non-linear, temperature-dependent expansion, and glass weave constraint, resin ductility, and moisture effects change below ambient. Extrapolating high-temperature data to -40°C or -55°C is unreliable, so direct sub-ambient measurement is required for accurate reliability assessment.
• What temperature range is typically used? Standard low-temperature programs span -65°C to +25°C. Automotive evaluations often focus on -40°C, military applications on -55°C, and space or research programs may extend to -196°C using liquid nitrogen cooling.
• Which standards apply to this test? Common references include ASTM E831 (TMA), ASTM E228 and ASTM D696 (dilatometry), and IPC-TM-650 methods 2.4.24 and 2.4.41 for laminate and substrate CTE measurement.
• What sample sizes and preparation are required? TMA in-plane specimens are typically 3 to 10 mm long with clean, parallel edges; Z-axis specimens are 0.3 to 3 mm thick. All samples are moisture-conditioned by baking and are tested in the as-received lay-up orientation.
• What CTE values are considered acceptable? Acceptance depends on package type. General-purpose organic substrates fall between 10 and 17 ppm/°C in-plane, large-body FCBGA substrates often specify below 10 ppm/°C, and glass or silicon-based substrates approach the 2.6 ppm/°C of the die. Matching the die CTE within a few ppm/°C minimizes low-temperature solder joint strain.
• How does low-temperature CTE affect solder joint reliability? A larger CTE gap between die and substrate produces higher differential contraction during cold excursions, accelerating fatigue crack initiation in solder joints and delamination at die-attach and underfill interfaces during repeated cycling.
• What does CTE hysteresis indicate? If contraction and expansion curves fail to retrace each other across repeated cold cycles, the material has likely developed microcracks, resin damage, or fiber-resin debonding, which is an early warning of latent field failures.